This paper introduces a peculiar approach of designing static random access memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% and 15% improvement in terms of total number of Cell counts and Area. Similarly, the proposed design structure realizes the overall power dissipation savings up to 35. 3% at maximum energy dissipation of circuit, 38. 6% at average energy dissipation of circuit, 36. 1% at minimum energy dissipation of circuit, 36. 4% at average energy dissipation of circuit and 40. 1% at average switching energy dissipation compared to the latest reported designs. The power analysis and structural analysis of the proposed design is compared with its state-of-the-art counterpart designs, using QCAPro and QCADesigner 2. 0. 3 tools. The proposed QCA based SRAM cell design can be taken as a base design in building an ultra-low power information generating systems like Microprocessors.

In this research article, an Ultra-low-power 1-bit SRAM cell is introduced using Tunneling Field Effect Transistor (TFET). This paper investigates feasible 6T SRAM configurations on improved N-type and P-type TFETs integrated on both InAs (Homojunction) and GaSb-InAs (Heterojunction) platforms. The voltage transfer characteristics and basic parameters of both Homo and Heterojunctions are examined and compared. The proposed TFET based SRAM enhances the stability in the hold, read, and write operations. This work evaluates the potential of TFET which can replace MOSFET due to the improved performance with low-power consumption, high speed, low sub-threshold slope, and supply voltage (VDD = 0.2 V). The results are correlated with CMOS 32nm technology. The proposed SRAM TFET cell is implemented using 30nm technology and simulated using an H-SPICE simulator with the help of Verilog-A models. The proposed SRAM TFET cell architecture achieves low power dissipation and attains high performance as compared to the CMOS and FINFET.

This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature decreases write mode failure. An access buffer seperates storage node from read access transistor to improve cell stability and prevent data-related leakage in read operation. Applying virtual ground also reduces the leakage. Furthermore, we design the cell control unit. The simulation results at VDD=0. 5V exhibit the effectiveness of our proposed cell compared with other counterparts which are suitable for bit interleaving structure. Comparison results on the proposed cell and 6T cell show our cell improved 70% in write power consumption and 90. 45% in read power consumption.

This paper presents analysis of the static Noise Margin (SNM), power dissipation, access time and dynamic noise margin of a novel low power proposed 8T static random access memory (SRAM) cell for read operations. In the proposed structure, two voltage sources are used, one is connected with the bit line and the other is connected with the bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. Simulation results for the read static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other SRAM cells, reported in dierent literatures. It is shown that the proposed SRAM cell has better static noise margin and dissipates less power in comparison to other SRAM cells. Analog and schematic simulations have been done in a 45 nm environment with the help of Microwind 3.1, using the BSimM4 model.

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Hash or B-Tree based composite indexes, are the two most commonly used techniques for searching and re-trieving data from memory. Although these techniques have a serious memory limitation, that restricts free-dom to search by any combination of single key/data attribute, that comprises the composite search key, the techniques are still accepted considering the trade o s with better performance on insert and update opera-tions. But when the data is semi-static, which does not change often, there is a need and scope for a better tech-nique that provides the exibility and freedom to e-ciently search by any possible key, without creating any composite index. This paper explains such algorithmic technique along with its data structures.